The present invention relates to a non-volatile memory cell and in particular to a method of forming a non-volatile memory cell by integrating an oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap to a diffusion region to enhance coupling of the source to the floating gate. The present invention also provides a novel non-volatile memory cell which includes, among other elements, an ONO capacitor merged with a polysilicon strap to a diffusion region, whereby enhanced coupling of the source to the floating gate is obtained.
As is known to one skilled in the art, non-volatile memory cells are types of memory devices that are capable of retaining stored information after the power supply has been removed. Memory cells of this type include: erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM). In EEPROM memory cells, programming or writing is achieved by injection of hot electrons from the substrate through an oxide layer in response to a high applied drain voltage. Erasure, on the other hand, is achieved by photoemission of hot electrons from the floating gate to the control gate and the substrate.
EEPROMs generally employ two element cells with two transistors. Programming and erasing are achieved by means of the Fowler-Nordheim effect which employs electrons that tunnel through the energy barrier at the silicon-silicon oxide interface and into the oxide conduction band. During xe2x80x9creadingxe2x80x9d of the memory cell, the state of the EEPROM cell is determined by current sensing.
In conventional non-volatile spilt-gate memory cells, a self-aligned source/drain implant is employed in order to reduce the cell size below 30 xcexcm2. In such cells, programming is achieved by channel injection of hot electrons, while erasing is achieved by the Fowler-Nordheim tunneling or photommission from the floating gate.
Conventional split gate memory cells made from prior art processes include a floating gate that is charged by injection of hot electrons from the channel region of the transistor. A control gate is formed over the floating gate to control the portion of the channel region between the floating gate and the source region in order to achieve split gate operation.
Moreover, in split gate memory devices, the floating gate is made to overlap the drain region of the device so that writing and programming may be implemented. When there is no overlap, or an actual underlap, writing cannot be effectuated with hot electron injections; thereby reducing the programming efficiency of the memory device. Additionally, in split gate memory devices, the control gate must overlap the floating gate and extend over the channel to overlap the source region so as to enable turning xe2x80x9conxe2x80x9d and driving the memory cell. In conventional split gate progressing, the source/drain regions are typically formed, i.e., implanted and activated, prior to poly gate formation. Such prior art processes, do not employ a fully self-aligned source/drain region; therefore the cell area size is extended and the transistor channel length increased.
In prior art split gate memory cells, any misalignment of the source relative to the floating gate affects the read current uniformity. In order to avoid misalignment, prior art non-volatile memory devices contain an overlap of the control gate to the source. Also, in some non-volatile memory devices, the drain is self-aligned to the floating gate, but the source region is not self-aligned to the floating gate; therefore, the channel length is not determinate. This, in turn, adversely affects current dispersion in the memory device during operation.
In cases wherein the total channel length is not a fixed distance, programming will also be adversely affected. If the total channel length varies, it is difficult to scale the dimensions of the layers used in forming the memory cell, thus high programming efficiency and cell reproducibility cannot be obtained. If, on the other hand, the length dimension is too large, the programming efficiency is not adequate, and the cell read current is reduced to the detriment of device operation. Additionally, when an overlap is provided, a substantial area of the cell is wasted and cell size becomes unnecessarily large.
In view of the drawbacks with prior art non-volatile memory devices, there is a continued need for developing a new and improved method of manufacturing a split gate non-volatile memory cell which can be scaled down to very-small geometries, while maintaining sufficient overlap between the floating gate and the source region as well as maintaining a functioning floating gate channel.
One object of the present invention is to provide a method of fabricating a floating gate non-volatile memory cell which has a geometry of about 0.5 xcexcm or less associated therewith.
Another object of the present invention is to provide a method of fabricating a non-volatile memory cell which has a sufficient overlapping region between the floating gate and the source diffusion, while maintaining a functional floating gate channel.
A further object of the present invention is to provide a method of fabricating a non-volatile memory cell which comprises a merged ONO capacitor and a polysilicon strap integrated to a diffusion region.
The above objects and advantages are achieved in the present invention by utilizing polysilicon spacers to define the source edge of the floating gate in a nitride trench defined over the floating gate polysilicon on an oxidized semiconductor substrate. More specifically, the above objects and advantages are achieved by integrating a merged ONO capacitor and a polysilicon strap to a diffusion region of the device. By integrating these elements, enhanced coupling of the source to the floating gate is obtained.
The inventive method comprises the steps of:
(a) forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a floating gate polysilicon layer, an oxide layer and a nitride layer;
(b) forming an opening in said film stack so as to expose a portion of said floating gate polysilicon layer;
(c) forming oxide spacers in said opening;
(d) forming an oxide-nitride-oxide capacitor in said opening;
(e) forming polysilicon spacers on said oxide-nitride-oxide capacitor;
(f) providing a contact hole in said opening so as to expose a portion of said substrate;
(g) forming an oxide liner in said contact hole and on said nitride layer of said film stack;
(h) forming a source region in said substrate;
(i) forming oxide spacers from said oxide liner;
(j) filling said opening and contact hole with doped polysilicon; and
(k) planarizing down to said nitride layer of said film stack.
The non-volatile memory device is the completed by using conventional processing techniques which may include:
(l) removing the nitride layer and said floating gate polysilicon layer of said film stack;
(m) forming a wordline gate oxide; and
(n) forming a wordline spacer about said wordline gate oxide.
The above method results in a non-volatile memory cell which comprises a substrate; and a source region formed in said substrate, said source region being self-aligned with an overlaying floating gate region, said floating gate region comprising an ONO capacitor merged with a polysilicon strap, and wherein said ONO capacitor and said polysilicon strap are integrated to said source region within the structure.